1. Field of the Invention
The embodiments of the invention generally relate to integrated circuit systems, and, more particularly, to stacked via integrated circuit structures.
2. Description of the Related Art
The use of stacked vias on resin filled plated thru-holes (RFPs) in build-up flip chip package ball grid array (FCPBGA) laminate chip carriers are known areas of high stress in high performance organic modules. The mismatch in the coefficient of thermal expansion (CTE) generally results in an area of high stress in the stacked vias on the RFPs. The stress tends to be higher when the number of stacked vias increases (1, 2, and 3 stacked vias). As the module performance requirements increase and higher wireability is needed, multi-high stacked vias are generally required in the design of most organic modules. However, failure at the stacked vias on RFP continues to be a significant problem with this technology leading to reduced reliability.
RFPs are formed by drilling holes in a laminate core structure and plating the inside of the holes with copper. Next, the remaining holes are filled with a filled epoxy resin, and a layer of copper is plated over the resin fill. After circuitizing the copper layer, which includes forming lines and a disk shaped RFP land over the RFP, a layer of dielectric material is applied, vias are formed in the dielectric layer using laser ablation, and the dielectric layer is circuitized using a pattern plating process. The result is a circuitized layer containing solid copper interconnect vias. At the top of this via is a relatively larger area of plated copper, called a land. Next, this process is repeated as many times as needed to build the structure (i.e., two additional times for a total of three build-up layers). At each step, there is a larger disk of copper plated over the via hole, called a via land, which allows for registration shifts in the next layer as the structure is built. These via lands are typically about 100 μm in diameter, while the RFP lands can be typically 250 μm in diameter.
An additional reliability concern is from mechanical damage to the module-through test, inspection, etc., after assembly. Furthermore, using improper handling techniques while inserting or removing modules from test sockets can put a strain on the BGA ball. Since the BGA balls are connected directly to the RFP cap through the stacked vias, this strain may result in a separation of the via stack from the RFP cap copper. Another common failure mode for stacked vias on RFPs is due to the lifting of the input/output (I/O) pad that the stacked via connect to, and the resulting tear-out of the underlying dielectric layer. Tear-out of the I/O pad is commonly observed for conventional stacked vias on RFPs. Tear-out commonly occurs when there are no copper planes under the I/O pad. Moreover, tear-out occurs where there are large openings in the planes below the BGA pad, and intermetallic fails occur when the planes below the BGA pads are connected to the via stack or have small clearance openings. Therefore, there remains a need for a novel via structure for enhanced organic module performance, which overcomes the limitations of the conventional structures.